This Pololu module enables galvanically isolated (electrically isolated), bidirectional communication between two IC devices, and comes with JST-SH (Qwiic/STEMMA QT compatible) connectors.

This isolation means current cannot flow from one side to the other, and incorrect connections or bad voltages on one side cannot propagate through to damage the device connected to other side. The module is based on the TI ISO1640B, which supports bidirectional data transfer up to 1.7 MHz. See the ISO1640BDR datasheet for more information.

This is the version with JST-SH (Qwiic/STEMMA QT compatible) connectors, allowing easy connections with JST-SH 4-pin cables. We also stock a version with no connectors, which may be better for compact projects with directly soldered wires.

Using the module

Each side must be powered separately: 3V to 5.5V should be supplied acrossVCC1andGND1, and 2.25V to 5.5V should be supplied acrossVCC2andGND2. The two sides are galvanically isolated (GND1 isNOTconnected to GND2).

SDA1andSCL1connect to the IC data and clock signals of one device, whileSDA2andSCL2connect to the IC data and clock signals of the other. Both the SDA and SCL connections are bidirectional, which allows for clock stretching. There are 10k pull-up resistors from SDA1 and SCL1 to VCC1 and from SDA2 and SCL2 to VCC2; for high-speed communication, external pull-up resistors can be added in parallel as necessary to make the pull-ups stronger.

Note:The two sides of the ISO1640 have different logic thresholds. In particular, SDA1 and SCL1 will only drive as low as 0.5V to 0.7V when the corresponding SDA2 or SCL2 are driven low, so it is important to ensure that the device connected to side 1 will recognize 0.7V as low. In the other direction, SDA2 and SCL2 will drive to between 0V and 0.4V when SDA1 and SCL1 are driven low. See theISO1640 datasheetfor more information.

Isolation/clearance considerations

Although the ISO1640 IC has an isolation rating of up to 3 kVRMS, please note that the board is made to be compact, and the tightest clearance (2 mm) is smaller than the 4 mm clearance of the IC package. The picture below shows the regions of tightest clearance (the larger pads are just structural pads for the connectors and are not electrically connected to anything):

Specifications

Resources

• Schematic
• Dimensions
• 3D Model (STEP)
• Drill guide
• TI ISO1640BDR datasheet